Semiconductor majors form alliance

,

and

have reached a preliminary agreement to co-operate on the creation and validation of high-level System-on-Chip (SoC) intellectual property (IP). Implementation and completion of this agreement is still subject to the successful conclusion of a contract between the partners.

The companies already work together as part of the Crolles2 Alliance in the research, development and industrialisation of CMOS process technologies. The Alliance partners see a bundling of effort in generation, validation and support of high-level SoC IP blocks as a ‘logical next step’. The goal is to shorten the time-to-market for the increasingly complex chips demanded by today’s systems.

The three Alliance partners plan to set up the Library and IP Partnership (LIPP) with operations across a number of sites. Potential sites include Grenoble, France, Eindhoven, The Netherlands, Austin, Texas and Bangalore and Noida in India, with headquarters in Eindhoven.