Scientists have made a memory device that combines silicon nanowires with a more traditional type of data-storage to make more reliable storage that can be integrated into commercial applications.
Scientists at the National Institute of Standards and Technology (NIST), George Mason University and Kwangwoon University in Korea developed the non-volatile memory hardware. In the device, nanowires are integrated with a higher-end type of non-volatile memory that is similar to flash, a layered structure known as semiconductor-oxide-nitride-oxide-semiconductor (SONOS) technology. The nanowires are positioned using a hands-off self-alignment technique, which could allow the production cost of large-scale devices to be lower than flash memory cards, which require more complicated fabrication methods.
The researchers grew the nanowires onto a layered oxide-nitride-oxide substrate. Applying a positive voltage across the wires causes electrons in the wires to tunnel down into the substrate, charging it. A negative voltage causes the electrons to tunnel back up into the wires. This process is the key to the device’s memory function. When fully charged, each nanowire device stores a single bit of information, either a ‘0’ or a ‘1’ depending on the position of the electrons. When no voltage is present, the stored information can be read.
The device combines the excellent electronic properties of nanowires with established technology, and has several characteristics that make it very promising for applications in non-volatile memory. For example, it has simple read, write, and erase capabilities. It boasts a large memory window, or the voltage range over which it stores information, which indicates good memory retention and a high resistance to disturbances from outside voltages. The device also has a large on/off current ratio, a property that allows the circuit to clearly distinguish between the ‘0’ and ‘1’ states.
Two advantages the NIST design may hold over alternative proposals for nanowire-based memory devices, the researchers say, are better stability at higher temperatures and easier integration into existing chip fabrication technology.
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