Designing microchip memories

As transistors on silicon chips get smaller, so tiny variations within their structures affect their performance and thus the reliability of the whole microchip. It is a problem that presents a huge barrier to the continued scaling of microchips and the development of ever more powerful computers.

To overcome this obstacle, the European Commission (EC) has established a taskforce to come up with ways of designing future microchip memories that take into account the variability and unreliability of nano-scale transistors.

The ’Tera-scale Reliable Adaptive Memory Systems’ (TRAMS) consortium includes Intel Iberia, Interuniversitair Micro-Elektronica Centrium, Glasgow University and the Universitat Politecnica de Catalunya, and is financed through the EU’s Framework Programme 7 (FP7) science-research fund.

Prof Asen Asenov of the Department of Electronic and Electrical Engineering is leading Glasgow University’s involvement in the project.

’If we are to continue to shrink the size of transistors in order to develop powerful circuits, we need fundamentally new approaches to circuit and system design that can take account of the variability within transistors. We hope this project will result in new chip-design paradigms for building reliable memory systems out of unreliable nano-scale components cheaply and effectively.’

Central to the project is simulation software developed by Prof Asenov in an earlier £5.3m Engineering and Physical Sciences Research Council eScience pilot project, called NanoCMOS.

The NanoCMOS simulations use grid computing, which uses the processor power of thousands of linked computers to simulate how hundreds of thousands of transistors, each with their own individual characterstics, will function within a circuit.

Prof Asenov and Glasgow University are setting up a company called Gold Standard Simulations to exploit the technology, which will be critical to the work of the TRAMS project, with all device design and simulation work being conducted at Glasgow.

In investigating design possibilities for future microchips, the team will focus on the future generation of CMOS microchip technologies - which will comprise transistors less than 16nm in size. The transistors will be designed and simulated exclusively at Glasgow University.

The TRAMS consortium will also consider what are known as ’Beyond CMOS’ technologies - nanowire transistors, quantum devices, carbon nanotubes and molecular electronics, which are expected to be as small as 5nm.

The project is expected to last three years.