IBM has begun producing chip-stacking technology in a manufacturing environment which allows chip components to be packaged much closer together for faster, smaller, and lower-power systems.
The breakthrough, known as ‘through-silicon-vias’, enables the move from horizontal 2D chip layouts to 3D chip stacking, which takes chips and memory devices that traditionally sit side-by-side on a silicon wafer and stacks them together on top of one another. The result is a compact sandwich of components that dramatically reduces the size of the overall chip package and boosts the speed at which data flows among the functions on the chip.
The new IBM method eliminates the need for long metal wires that connect current 2D chips together, instead relying on through-silicon-vias, which are essentially vertical connections etched through the silicon wafer and filled with metal. These vias allow multiple chips to be stacked together, allowing greater amounts of information to be passed between the chips.
The technique shortens the distance information on a chip needs to travel by 1000 times, and allows for the addition of up to 100 times more channels, or pathways, for that information to flow compared to 2D chips.
IBM is already running chips using the through-silicon-via technology in its manufacturing line and will begin sampling chips using this method to customers in the second half of 2007, with production in 2008. The first application of this through-silicon-via technology will be in wireless communications chips that will go into power amplifiers for wireless LAN and cellular applications. 3D technology will also be applied to a wide range of other applications including IBM’s high-performance server and supercomputing chips.
Chips are stacked for IBM
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