The demonstrations were carried out by researchers from the National University of Singapore (NUS) and industry partners Soitec and NXP Semiconductors
The innovation has been demonstrated in fully-depleted silicon-on-insulator (FD-SOI) technology, and can be applied to the design and fabrication of advanced semiconductor components for AI applications.
According to NUS, the new chip technology has the potential to extend the battery life of wearables and smart objects by a factor of 10, support intense computational workloads for use in Internet of Things applications, and halve the power consumption associated with wireless communications with the cloud.
The new suite of chip technologies will be promoted through the FD-SOI & IoT Industry Consortium to accelerate industry adoption by lowering the design barrier to entry in FD-SOI chips.
An industry workshop titled 'Next-gen energy-efficient FD-SOI systems' was held on May 3, 2024 for participants from the industry and research community to share and discuss the latest developments in FD-SOI technologies, and showcase the new capabilities with demonstrations.
In a statement, Professor Massimo Alioto, from the NUS College of Design and Engineering’s Department of Electrical and Computer Engineering, said: “IoT devices often operate on a very limited power budget, and hence require extremely low average power to efficiently perform regular tasks such as physical signal monitoring. At the same time, high peak performance is demanded to process occasional signal events with computationally-intensive AI algorithms. Our research uniquely allows us to simultaneously reduce the average power and improve the peak performance.”
“The applications are wide-ranging and include smart cities, smart buildings, Industry 4.0, wearables and smart logistics. The remarkable energy improvements obtained in the FD-fAbrICS program are a game changer in the area of battery-powered AI devices, as they ultimately allow us to move intelligence from conventional cloud to smart miniaturised devices,” added Prof Alioto, who is also the Director of the FD-fAbrICS (FD-SOI Always-on Intelligent & Connected Systems) joint lab where the new suite of technologies was engineered.
Research conducted by the NUS FD-fAbrICS joint lab showed that their FD-SOI chip technology can be deployed at scale with enhanced design and system integration productivity for lower cost, faster market reach, and rapid industry adoption.
The NUS team is said to be looking into developing new classes of intelligent and connected silicon systems that could support larger AI model sizes for generative AI applications.
NUS added that the resulting decentralisation of AI computation from cloud to distributed devices will simultaneously preserve privacy, keep latency at a minimum, and avoid wireless data deluge under the simultaneous presence of a plethora of devices.
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Does The Engineer have a translation for the Chinese heading to this piece?!